Today a major barrier to full realization of the advantages offered by widely used highly integrated circuits is the packaging technology. Connecting, cooling, and housing of circuits is referred to as packaging. The integration density of electronic and opto-electronic circuits is growing very fast. Today the integration of thousands of transistors, capacitors, resistors, and other elements on one chip is possible. There is a similar integration trend in the area of opto-electronic devices.
With increasing integration density, the heating of integrated circuits becomes more and more a problem. The power density and therewith the heating of these circuits increases. The performance of electronic and opto-electronic elements is affected by the temperature to such a degree that stable temperatures become of fundamental importance for reliable operation. Overheating of semiconductors and semiconductor devices as well, leads to destruction of the same. The fact that the circuit density is rising faster than the power consumed by the individual circuits can be reduced, requires increasing care in the dissipation of thermal energy, and homogeneous and effective cooling of integrated circuits becomes more important.
Basically, two different methods for the cooling of integrated circuits are known in the art. The first one, known as thermal conduction, is based on the physical principle (following thermodynamic concepts), that heat flows along a thermal gradient, from one part of a body at a higher temperature, to another part of a body at a lower temperature. The second method for removing heat from a heat source uses convection, where the heat is transferred from the source to a cooling fluid which passes the heat source. Fluid cooling systems are very bulky and the motor-driven pumps which are necessary for the circulation of the fluid are susceptible to trouble and may cause electro-magnetic disturbances.
More reliable, smaller, and simpler cooling structures are based on the first mentioned thermal conduction. Different cooling structures, based on the principle of conduction, are known in the art. FIG. 1 shows a cross section of a prior art chip package module wherein a semiconductor chip 10, with an active layer 11, is secured to a substrate 12. The electronic elements situated in the active layer 11, are electrically connected via bond wires 15, to pins 14. The chip 10, mounted on substrate 12, is protected by a heat sink metal cap 13, which is secured to the substrate 12. The heat developed by the electronic elements in the active layer 11, flows through the chip 10, and the substrate 12, to the metal cap 13, as illustrated by the heat flux arrows 16. As illustrated in FIG. 1, the chip 10, is mounted such that the active layer 11, is oriented upward and the heat developed in the active layer has to flow through the chip 10, and substrate 12, to the heat sink 13.
Another cooling structure of the prior art is shown in FIG. 2. A semiconductor chip 20, with active layer 21, is mounted on solder balls 24, such that the active layer 21, is oriented downwards. The electronic elements of the active layer 21, are electronically connected via conductive lines 23, and conductive structures 22, such as vias, to metal pins 14. The conductive structures 22, are situated on a single or multilayer substrate 25, which is secured to a metal cap 13. The substrate 25, can be formed of inorganic resins, ceramic, or any suitable dielectric material. The upper part of the module of FIG. 2, includes a flexible thermal bridge 26, extending between the cap 13, and the backside surface of the chip 20. The heat flux 16, passes through the chip 20, and the thermal bridge 26, to the cap 13. In this structure, the active layer 21, is, in contrast to the arrangement of FIG. 1, oriented downward but the heat, nevertheless, has to flow from said active layer 21, through the chip 20, and then via a thermal bridge 26 to the heat sink metal cap 13.
These cooling structures, illustrated in FIG. 1 and FIG. 2, are in principle described, for example on pages 48, 49 and 338, in "Microelectronics Packaging Handbook", edited by R. R. Tummala and E. J. Rymaszewski, publisher Van Nostrand Reinhold (1989), and in the article "Semiconductor Module With Improved Air Cooling", IBM Technical Disclosure Bulletin, Vol. 20, No. 5, page 1768 (October 1977), respectively, and the disclosures of which are incorporated herein by reference.
A great number of similar cooling structures based on the above described principles are known in the art, as there are for example, the European Patent EP 97782, which corresponds to U.S. Pat. No. 4,479,140, entitled "Thermal Conduction Element For Conducting Heat From Semiconductor Devices To A Cold Plate", the article "Bump Internal-Thermal Enhancement", IBM Technical Disclosure Bulletin, Vol. 27, No. 7B, pp. 4413-4415, (December 1984), and the article "Chip/Can Conduction Path", IBM Technical Disclosure Bulletin, Vol. 20, No. 8, page 3223 (January 1978). The disclosure of all of these references is incorporated herein by reference.
It is known in the art that lasers with high power can be cooled by mounting them junction-sidedown and soldering them onto a heat sink, e.g. a metal cooling structure. The active elements are directly thermally coupled to the heat sink. Disadvantages of this packaging method are that the heat sink has to be structured and this is time consuming and expensive alignments become necessary. A further disadvantage of this type of mounting is, that Junction-side-down mounting is not possible if optical input/output ports are required.
One main disadvantage of all the above described and other structures known to the applicant is, that the heat has to flow from the heat sources through the chip from where it is eliminated via a substrate or a thermal bridge (with the exception of the above described junction-side-down mounted lasers). The thermal resistance between the heat developing elements in the active layer and the heat sink is substantial, mainly caused by the thickness of the chip and its poor thermal conductivity, resulting in overheating and reduced reliability of these chips.